The Mux: Difference between revisions
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The data is shifted in on the rising edge of the clock line. This clock line has multiple destinations and also clocks the Mux ICs in the rack and the 74HC597 ICs in the controller used to shift the button states into the PIC. Once the LED data has been shifted to the correct position within the shift registers, a rising edge on the Storage Register line moves this data to the outputs of the ICs, and hence the LEDs/Buzzer. | |||
Five 74HC597 ICs are used to create a single parallel-to-serial converter. The order of buttons fed into the PIC is that same as the order of the LED data is shifted out of the PIC (see above). The only difference is instead of the 3 unused LED states there are the three remaining buttons on the controller. The data is shifted on the rising edge on the shared clock line (see above). Before shifting of the data commences the Parallel Load line must be cleared, a rising edge must occur on the Storage Clock line, and then the Parallel Load line must be set. | |||
The state of the Mux ICs in the rack unit is controlled via 3 lines: Chip Select (CS), Clock and data. Before communication with the ICs begins the CS must be cleared (active low). 64 bits of data must then be shifted into the the ICs (clock active rising edge) before setting CS to select the new inputs. The 32x4 Mux is generated using four 8x4 ICs with their outputs commoned together. Therefore the data is organised into four blocks of 16-bits, with each block controlling one of these ICs. For information on the order in which to clock in data, see the datasheet [[https://ystv.york.ac.uk/~documents/docs_resources/StationDocumentation/MAX458-MAX459.pdf]]. Importantly only one of the Mux ICs should ever be driving each output from the mux, with the outputs on the other three ICs all disabled. | |||